Scan design is used in design-for-test (DFT) for digital circuits. Scan design provides test access to improve testability of the a device under test (DUT) and reduces test cost. An example of scan design is depicted in prior art FIG. 1. A purpose of scan design is to provide test access to increase testability of combinational circuit. The scan design may replace normal internal registers with scan registers. The scan register adds a signal path called a scan path to the normal register so that the register can directly be accessed externally. The scan path can be active if a scan enable (SE) signal is set to, for example, a logical high signal (which can be referred to as 1). Otherwise, the normal path is selected and the scan register functions as a normal register. The scan path for scan registers is connected in serial fashion to form a shift register called scan chain. Since the time to load and unload scan chain dominates overall test time, there can be multiple scan chains in parallel to reduce test time. The scan chains can be accessed internally by on-chip test circuitry such as build-in self test (BIST) and/or by an external tester.
Referring to FIG. 1, an assembly 10 in an integrated circuit chip includes a scan chain 14 including multiplexers 20-1 . . . 20-N and registers (such as flip-flops) 22-1 . . . 22-N coupled to circuits in combination logic 18. Registers 22-1 . . . 22-N are clocked by a clock signal CLK. First, the scan path is selected (SE=1), and an input test pattern (SI) is shifted into the scan chains to initialize the scan registers. The output of registers 22-1 . . . 22-N is available to combination logic such as one or more of logic gates 30, 36, and 40. Second, the normal functional path is selected and primary input (PI) is forced. Then, the primary output (PO) is measured and compared against expected output. Certain outputs of combination logic 18 such as outputs of gates 30, 36, 40, and/or 42 may be provided as the 0 input to multiplexers 20-1 . . . 20-N which provide them to inputs of registers 22-1 . . . 22-N when SE=0. The clock (CLK) pulse is applied to capture the test response of combinational logic 18 into the registers. The scan path is then selected (SE=1) and the test response (test vector) is shifted out (scan out SO) while a next input test pattern is shifted in. The obtained test response SO is compared with expected response in order to decide whether the DUT is good or bad. This process repeats until all test patterns are exercised. Scan input periods are when SE=1 and capture periods are when SE=0.
FIG. 2 illustrates a scan chain segment 46 including multiple multiplexers and registers as shown in the scan chain of FIG. 1 and a lock-up latch 48 to receive the output of scan chain segment 46 and hold it until the clock transitions low. Lockup latches are used to tolerate clock skew up to, for example, a half of clock period.
The peak power problem during scan shift is illustrated in prior art FIG. 3 which includes registers 52-1, 52-2, and 52-3 in one chain clocked by a CLK1 signal, and registers 54-1 and 54-2 in another scan chain clocked by a CLK2 signal, each coupled to combinational logic 50. (Multiplexers are not illustrated because of limited space.) Of course, the chains may be much larger. When the scan chains are loaded, a potentially excessive number of transitions can be injected into the combinational logic from the scan registers. Those injected transitions can cause outputs of logic gates to switch and create more transitions within the DUT.
Creation of transitions requires power which is supplied from the supply voltage (VDD). Such excessive instantaneous power demand can create supply voltage noise such as is shown in FIG. 4. The resulted supply voltage noise may alter the operating frequency of the DUT and may cause timing problems such as hold-time violations. The resulted timing problems may fail the intended test function and lead to incorrect test decision.
To help with this problem, prior art assemblies such as in FIG. 3 provide the scan shift clocks in different phases (at different times), called clock skew. For example, in FIG. 5, shift clocks CLK1, CLK2, . . . CLKn have rising edges at different times. However, prior art circuits have not used clock skew effectively.